1. Field of the Invention
This invention relates to a novel and improved device for testing digital electronic circuits. Particularly, the invention relates to a device for automatically testing integrated circuits, printed circuit boards incorporating one or more integrated circuits, and even larger and more complex systems.
2. Description of the Prior Art
Testing of electronic circuits becomes more and more important as the circuits become more complex. This applies not only to integrated circuits but also to boards which usually combine several integrated circuits, or even to larger systems which combine circuit boards and a plurality of other components. Testing is required not only when the product has been manufactured, but also after it has been installed in the field. Testing of a digital circuit should be made as simple and easy as possible so that it can be performed even by the user. In such testing, it is important to determine whether or not a given digital circuit meets a required performance specification.
In recent years, testing devices have been designed for integrated circuits. The basic idea is to equip the integrated circuit under consideration with test aids supporting a self-test of the electronic product (Built-In Test).
From the "Proceedings, 1979 IEEE Test Conference", Cherry Hill, N.J., Session 2, pages 37 to 41, it is known to use the so-called "Built-In Logic Block Observation Techniques".
Testing devices according to these "Techniques" primarily deal with testing of integrated circuits. In one version (see "Proceedings", supra, FIG. 1) of the known testing device, digital circuits are tested by stimulating the inputs of the circuit under test with an appropriate sequence of input words called test patterns. The circuit under test reacts to this stimulus by issuing a sequence of output words called test data. Two steps are taken for the detection of a hardware fault in the circuit under test: First, the fault is detected at the outputs of the circuit under test. This is achieved by comparison means. When a fault is present, the test data sequence issued by the circuit under test differs from a predetermined nomimal sequence that a fault-free circuit would have issued. A preferred method for comparing the test data with the nominal data is based on cyclic coding and a tachnique known as "signature analysis". Second, the fact that the measured test data sequence does not equal to the nominal sequence is registered and transformed into a fault message by test data evaluating circuitry.
In the "Proceedings, 1979 IEEE Test Conference", supra, see FIG. 6, is also disclosed a multi-functional subsystem called a "Built-In Logic Block Observer" or "BILBO" for short. A BILBO can be used for data transfer and fault detection purposes in complex digital circuits. The BILBO is composed of a flip-flop register row and some additional gates for shifting and feed-back operations. In particular, eight flip-flops are normally provided, the inputs of which are each connected to a gate combination. Each gate combination comprises a NOR gate, an Exclusive OR gate and an AND gate. Feed-back is achieved with three Exclusive OR gates. A first control input signal is applied to the first input of each of the AND gates, and a second input signal is applied to the first input of each of the NOR gates. The outputs of a NOR gate and an AND gate are connected to the inputs of an Exclusive OR gate. Input data are supplied to the second inputs of the AND gates. From the flip-flops are derived output signals and the complimented output signals.
The BILBO operates in four different modes. In the first mode, it acts as a latch. In the second mode, it works as a linear shift register. Data are serially clocked into the register while the register contents may be simultaneously read at the outputs. In the third mode, the BILBO is functionally converted into a multiple-input signature register. In this third mode, the BILBO may be used for performing parallel signature analysis. In the fourth mode, the flip-flops of the register are reset.
Two BILBO's can be used for testing a circuit in a modular bus oriented design (see "Proceedings, 1979 IEEE Test Conference," supra, FIG. 7). However, details of the connection between the BILBO's and the circuit under test are not given.
In the "Proceedings, 1977 Semiconductor Test Symposium", Oct. 25-27, 1977, Cherry Hill, pp. 19 to 27, are disclosed two concepts for designing digital circuits in connecting with testing. The first concept consists of designing such that correct operation is not dependent on live time, full time or minimum delay of the individual circuit. The only dependency is that the total delays through a number of levels is less than some known value. This technique is known as "Level Sensitive Design". The second concept consists of designing all internal storage elements (other than memory arrays) such that they can also operate as shift registers. Networks which have both of these attributes are known as "Level Sensitive Scan Designs" or "LSSD". Once a design has this structure, random test patterns can be applied to this network without regard to the sequential nature of the network. "LSSD" is an improvement of the so-called scan path techniques. Details of the scan path techniques are disclosed in U.S. Pat. Nos. 3,783,254, 3,761,695 and 3,784,907.